A technology in which data is transmitted between integrated circuits and between information processing devices is known. When the speed at which data is transmitted is raised using such a technology, an error is likely to occur on the transmission path. On the assumption that errors probabilistically occur on the transmission path, a data transmission scheme is designed so as to permit errors that occur with a frequency defined in advance. Then, in the information processing device to which such a transmission scheme is applied, when the frequency at which errors have occurred exceeds a permissible frequency, it is determined that a failure has occurred on the transmission path.
For example, a serializer/deserializer (SerDes) transmission path for performing transmission of date by converting parallel data to serial data is designed such that the bit error rate obtained by dividing the number of bits having errors by the number of bits of transmitted data is equal to or less than 10−12. An information processing device that transmits data through a SerDes transmission path determines that a failure has occurred on the transmission path, when the bit error rate within a predetermined time interval is equal to or greater than 10−12. In another example, an information processing device counts the number of errors that have occurred, in each predetermined time interval, and determines that a failure has occurred on the transmission path when the counted number exceeds a predetermined threshold.
Japanese Laid-open Patent Publication No. 2000-101550 and Japanese Laid-open Patent Publication No. 2000-250896 disclose related art techniques.